1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device and, more particularly, to a synchronous DRAM.
2. Description of the Related Art
As a memory LSI which reduces or eliminates an access gap between a microprocessor and a memory, a synchronous memory has recently been proposed. A synchronous memory performs an input/output operation in synchronization with an external clock and thus has an increased data transfer rate.
A synchronous DRAM (hereinafter, "SDRAM") is one type of such synchronous memories. FIG. 4 is a block diagram illustrating a conventional synchronous DRAM.
The SDRAM performs a command setting operation and an input/output operation in synchronization with a rising edge of an externally supplied clock CLK. While the access time of an SDRAM for a first data point is substantially the same as that of a non-synchronous DRAM, an SDRAM is capable of reading a second and subsequent data points at a higher speed (e.g., a data point per clock cycle). The SDRAM includes a memory cell array 410 for a bank BANK0 and another memory cell array 420 for another bank BANK1. Data can be read out alternately in blocks of four words from the memory cell array 410 and from the memory cell array 420, for example, while effectively eliminating a precharge period and accessing different row addresses without an interruption.
The SDRAM has two modes of refresh operations, i.e., an auto-refresh operation and a self-refresh operation. FIG. 5 is a timing diagram illustrating a read/write operation and an auto-refresh operation of the SDRAM. FIG. 5 illustrates such operations compliant with a JEDEC (Joint Electron Device Engineering Council) standard where the burst length is 4 and the CAS latency is 2. An operation of the conventional SDRAM will be described below with reference to FIGS. 4 and 5.
The bit lines of the memory cell array 410 are precharged before time t0. In the following description, a designation such as "(t0)" refers to a series of operations which starts at time t0.
(t0)
At time t0, a chip select signal *CS and a row address strobe signal *RAS are at a low level, and a column address strobe signal *CAS and a write enable signal *WE are at a high level, thereby initiating an active operation. In particular, an address input signal AD is stored in a row address buffer 411 as a row address RA0. The row address RA0 is decoded by a row decoder 412, and one of the word lines in the memory cell array 410 is selected so as to read out the contents of a row of memory cells onto the bit lines. Then, data on each bit line is amplified by a sense amplifier 413.
(t2)
At time t2, the chip select signal *CS and the column address strobe signal *CAS are at a low level, and the row address strobe signal *RAS and the write enable signal *WE are at a high level, thereby initiating a read operation. In particular, an address input signal AD is stored in a column address buffer 415 as a column address CA0. The column address CA0 is decoded by a column decoder 416, whereby data D0 on a bit line which is selected according to the output from the column decoder 416 is supplied to an input/output circuit 430 via a column switch circuit 414. The data D0 is stored in, and then output from, a latch circuit in the input/output circuit 430.
(t4)
At time t4, the data D0 output from the DRAM is read by an external unit. A clock is supplied to a column address counter (not shown) in the column address buffer 415 so as to increment the column address. Data D1 on another bit line which is selected according to the column address is supplied to the input/output circuit 430 via the column switch circuit 414. The data D1 is stored in, and then output from, a latch circuit in the input/output circuit 430. Thereafter, substantially the same operation as that at time t4 is repeated until time t7. Thus, consecutive four words of data, i.e., the data D0 to D3, are output from the input/output circuit 430 during the period t4-t7.
(t6)
At time t6, the bit lines of the memory cell array 410 are precharged in preparation for the next access. In particular, at time t6, the chip select signal *CS, the row address strobe signal *RAS and the write enable signal *WE are at a low level, and the column address strobe signal *CAS is at a high level, thereby initiating a precharge operation.
(t8)
At time t8, the chip select signal *CS, the row address strobe signal *RAS and the column address strobe signal *CAS are at a low level, and the write enable signal *WE is at a high level, thereby initiating an auto-refresh operation. In the auto-refresh operation, a refresh address is produced by an internal refresh counter 417 so as to refresh a row of memory cells corresponding to the refresh address. In particular, the refresh address is stored in the row address buffer 411 and decoded by the row decoder 412, and one of the word lines in the memory cell array 410 is selected so as to read out the contents of a row of memory cells onto the bit lines. Then, data on each bit line is amplified by the sense amplifier 413 and re-written in one of the memory cells along the row. Then, the bit lines are automatically precharged. Each time an auto-refresh operation is performed, the refresh address output from the internal refresh counter 417 is updated. Thus, memory cells of new row addresses are successively refreshed.
According to the above-described refresh method compliant with a JEDEC standard, a plurality of memory banks are alternately refreshed. The memory banks cannot be refreshed simultaneously with a read/write operation.
A technique for refreshing different memory banks independently from and simultaneously with a memory access operation is disclosed in, for example, Japanese Laid-Open Publication Nos. 7-226077, 8-77769 and 9-139074.
FIG. 6 is a block diagram (FIG. 1 of Japanese Laid-Open Publication No. 9-139074) illustrating an SDRAM according to an example disclosed in Japanese Laid-Open Publication No. 9-139074. The SDRAM includes a memory cell array 200A forming a memory bank A and another memory cell array 200B forming another memory bank B. Each of the memory cell arrays 200A and 200B includes dynamic memory cells arranged in a matrix. Each memory cell includes a capacitor for storing data and a MOS transistor. The gate of the MOS transistor is coupled to a word line (not shown) and the drain thereof is connected to a complementary bit line (not shown).
In the memory cell array 200A, one of a plurality of word lines is driven to a selected level according to the results of a decoding operation on the row address signal by a row decoder 201A. The complementary bit line (not shown) of the memory cell array 200A is coupled to a sense amplifier/column selection circuit 202A. A sense amplifier in the sense amplifier/column selection circuit 202A is an amplifier circuit for detecting and amplifying a small potential difference which appears on each complementary bit line when reading out data from a memory cell. A column switch circuit in the sense amplifier/column selection circuit 202A is a switch circuit for individually selecting a complementary bit line and electrically connecting the selected complementary bit line to a complementary common bit line 204. The column switch circuit is selectively operated based on the results of a decoding operation on a column address signal supplied from a column decoder 203A.
Similarly, the memory cell array 200B includes a row decoder 201B, a sense amplifier and column selection circuit 202B and a column decoder 203B. The complementary common bit line 204 is connected to an output terminal of an input buffer 210 and to an input terminal of an output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 8 bits of data input/output terminals I/O 0-I/O 7.
A row address signal and a column address signal supplied from address input terminals A0-A11 are received by a column address buffer 205 and a row address buffer 206, respectively, in an address multiplexed manner. The supplied address signals are stored in the respective buffers. In a refresh operation mode, the row address buffer 206 receives a refresh address signal output from a refresh counter 208 as a row address signal. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs, to the column decoders 203A and 203B, either the column address signal as the preset data or a value obtained by successively incrementing the column address signal, according to the operation mode being specified by a command.
A controller 212 receives an external control signal (such as a clock signal CLK, a clock enable signal CKE, a chip select signal CS bar, a column address strobe signal CAS bar, a row address strobe signal RAS bar, a write enable signal WE bar, and a data input/output mask control signal DQM) and control data from the address input terminals A0-A11. The signals which may be supplied to the controller 212 are not limited to the above. The controller 212 produces an internal timing signal for controlling the operation mode of the SDRAM and the operation of the above-described circuit blocks, based on a change in level of these signals and the timing thereof. For this operation, the controller 212 includes a control logic (not shown) and a mode register 30.
The clock signal CLK is used as a master clock for the SDRAM. The other externally input signals are latched in synchronization with a rising edge of the internal clock signal CLK. The chip select signal CS bar indicates, by its low level, a start of a command input cycle. The signals RAS bar, CAS bar and WE bar have different functions than those of the corresponding signals used in an ordinary DRAM, and they are used when setting a command cycle. The clock enable signal CKE is a signal which indicates a validity of the next clock signal. The rising edge of the next clock signal CLK is assumed to be valid when the signal CKE is at a high level, and invalid when it is at a low level. Although not shown In the figure, the controller 212 also receives an external control signal for performing an output enable control for the output buffer 211 in a read mode. For example, the output buffer 211 has a high output impedance when this signal is at a high level.
The row address signal is defined by the respective levels at the address input terminals A0-A10 during a bank active command cycle which starts in synchronization with a rising edge of the clock signal CLK (internal clock signal). The input at the address input terminal A11 is considered as a bank selection signal during the bank active command cycle. In particular, the memory bank A and the memory bank B may be selected when the input at the address input terminal A11 is low and high, respectively.
The selection between/among memory banks can be performed by various methods including, but are not limited to: activating only the row decoder of the selected memory bank; unselecting all of the column switch circuits of the non-selected memory bank; and connecting only the selected memory bank to the input buffer 210 and to the output buffer 211.
The input at the address input terminal A10 during a precharge command cycle indicates the mode of precharge operation for a complementary bit line, or the like. The input at the terminal A10 being at a high level indicates that both memory banks are to be precharged, whereas the input at the terminal A10 being at a low level indicates that only one of the memory banks specified by the input at the terminal A11 is to be precharged.
The column address signal is defined by the respective levels at the address input terminals A0-A8 during a read or write command cycle (i.e., the cycle of a column address read command or a column address write command to be described later) which starts in synchronization with a rising edge of the clock signal CLK (internal clock signal). The column address defined as described above is used as a start address for a burst access operation.
The SDRAM has two different refresh commands as follows.
(1) Refresh Command 1
Refresh command 1 is a command which is required to start an auto-refresh operation. Refresh command 1 is issued when the signals CS bar, RAS bar and CAS bar are at a low level while the signals WE bar and CKE are at a high level. This auto-refresh command 1 simultaneously refreshes the two memory cell arrays 200A and 200B (the memory banks A and B) at once.
(2) Refresh Command 2
Refresh command 2 is a command which is required to start an auto-refresh operation for each memory bank. Unlike refresh command 1, refresh command 2 is issued, for example, when the signals CS bar, RAS bar, CAS bar, WE bar and CKE are at a low level. This auto-refresh command 2 references a particular bit in the mode register 30. For example, the memory cell array 200A is refreshed when the bit is "0", whereas the memory cell array 200B is refreshed when the particular bit is "1". Alternatively, the memory cell array 200A may be refreshed when the signal DQM, for example, is at a low level, while refreshing the memory cell array 200B when the signal DQM is at a high level.
In a refresh operation for an SDRAM as illustrated in FIG. 6, only a row address selection is performed. In particular, an address signal produced by the refresh counter 208, instead of the external address signal, is received by the row address buffer 206. Then, when refresh command 1 as described above is input, a word line selection operation and a sense amplification operation are performed for both of the memory cell arrays 200A and 200B. In particular, data stored in a dynamic memory cell which is connected to a selected word line in each of the two memory cell arrays 200A and 200B is sensed and amplified by the sense amplifier, and the amplified data is re-written in the same memory cell (i.e., refreshed). Alternatively, when refresh command 2 as described above is input, a word line selection operation and a sense amplification operation are performed for one of the memory cell arrays 200A and 200B which is specified by the signal DQM or the mode register.
While the memory cell array 200A (memory bank A), for example, is being refreshed in response to refresh command 2, a read/write operation may be performed for the other memory cell array 200B (memory bank B) in response to another command. For example, in the burst mode as described above, if the word line selection operation for the memory cell array 200B (memory bank B) has already been completed, a read/write operation is performed according to the address which is produced by the column address counter 207 provided in the memory cell array 200B.
However, according to the above-described conventional refresh method compliant with a JEDEC standard, a plurality of memory banks are alternately refreshed, and the memory banks cannot be refreshed simultaneously with a read/write operation. This is because it is not possible to externally control which bank is refreshed. Moreover, when a refresh operation is performed simultaneously with a read/write operation for the same bank, data from one row may collide with data from another row, thereby losing the data.
Japanese Laid-Open Publication Nos. 7-226077 and 8-77769 disclose a refresh method in which a particular bank can be specified. According to this refresh method, it is possible to perform a refresh operation for one bank while simultaneously performing an access operation such as a read/write operation for another bank. However, for the same reason as described above, a bank cannot be refreshed while a read/write operation is simultaneously performed for the same bank.